\doxysection{TIM\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_t_i_m___type_def}{}\label{struct_t_i_m___type_def}\index{TIM\_TypeDef@{TIM\_TypeDef}}


TIM.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_a9dafc8b03e8497203a8bb395db865328}{CR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_a6b1ae85138ed91686bf63699c61ef835}{CR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_a67d30593bcb68b98186ebe5bc8dc34b1}{SMCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}{DIER}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}{SR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_a04248d87f48303fd2267810104a7878d}{EGR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_a0f2291e7efdf3222689ef13e9be2ea4a}{CCMR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_aa8129ca70a2232c91c8cfcaf375249f6}{CCMR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_ad7271cc1eec9ef16e4ee5401626c0b3b}{CCER}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_a6fdd2a7fb88d28670b472aaac0d9d262}{CNT}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_ad03c852f58077a11e75f8af42fa6d921}{PSC}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_a6a42766a6ca3c7fe10a810ebd6b9d627}{ARR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_ad432e2a315abf68e6c295fb4ebc37534}{RCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_a0dd9c06729a5eb6179c6d0d60faca7ed}{CCR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_a4d1171e9a61538424b8ef1f2571986d0}{CCR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_ac83441bfb8d0287080dcbd945a272a74}{CCR3}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_a5ba381c3f312fdf5e0b4119641b3b0aa}{CCR4}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_a137d3523b60951eca1e4130257b2b23d}{BDTR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_a7efe9ea8067044cac449ada756ebc2d1}{DCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_afb7114ac49dba07ba5d250c507dbf23d}{DMAR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_ad6bf779ed80e96e9b3bda4c2dc3a1a6b}{RESERVED1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_ac0dcd8f9118b07b16cd79d03cb1a0904}{CCMR3}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_af30dc563e6c1b7b7e01e393feb484080}{CCR5}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_a374f851b5f1097a3ebd3f494ded6512a}{CCR6}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_a7a81e7aac9bef80b126097f8e9f36d07}{AF1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_a1e2d623b6e3ef17672550a56cb01354f}{AF2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_t_i_m___type_def_a48ce9972eb643ae4f34bd75a0b931ad4}{TISEL}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
TIM. 

\label{doc-variable-members}
\Hypertarget{struct_t_i_m___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_t_i_m___type_def_a7a81e7aac9bef80b126097f8e9f36d07}\index{TIM\_TypeDef@{TIM\_TypeDef}!AF1@{AF1}}
\index{AF1@{AF1}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{AF1}{AF1}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_a7a81e7aac9bef80b126097f8e9f36d07} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+AF1}

TIM alternate function option register 1, Address offset\+: 0x60 \Hypertarget{struct_t_i_m___type_def_a1e2d623b6e3ef17672550a56cb01354f}\index{TIM\_TypeDef@{TIM\_TypeDef}!AF2@{AF2}}
\index{AF2@{AF2}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{AF2}{AF2}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_a1e2d623b6e3ef17672550a56cb01354f} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+AF2}

TIM alternate function option register 2, Address offset\+: 0x64 \Hypertarget{struct_t_i_m___type_def_a6a42766a6ca3c7fe10a810ebd6b9d627}\index{TIM\_TypeDef@{TIM\_TypeDef}!ARR@{ARR}}
\index{ARR@{ARR}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ARR}{ARR}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_a6a42766a6ca3c7fe10a810ebd6b9d627} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+ARR}

TIM auto-\/reload register, Address offset\+: 0x2C \Hypertarget{struct_t_i_m___type_def_a137d3523b60951eca1e4130257b2b23d}\index{TIM\_TypeDef@{TIM\_TypeDef}!BDTR@{BDTR}}
\index{BDTR@{BDTR}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BDTR}{BDTR}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_a137d3523b60951eca1e4130257b2b23d} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+BDTR}

TIM break and dead-\/time register, Address offset\+: 0x44 \Hypertarget{struct_t_i_m___type_def_ad7271cc1eec9ef16e4ee5401626c0b3b}\index{TIM\_TypeDef@{TIM\_TypeDef}!CCER@{CCER}}
\index{CCER@{CCER}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CCER}{CCER}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_ad7271cc1eec9ef16e4ee5401626c0b3b} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+CCER}

TIM capture/compare enable register, Address offset\+: 0x20 \Hypertarget{struct_t_i_m___type_def_a0f2291e7efdf3222689ef13e9be2ea4a}\index{TIM\_TypeDef@{TIM\_TypeDef}!CCMR1@{CCMR1}}
\index{CCMR1@{CCMR1}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CCMR1}{CCMR1}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_a0f2291e7efdf3222689ef13e9be2ea4a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+CCMR1}

TIM capture/compare mode register 1, Address offset\+: 0x18 \Hypertarget{struct_t_i_m___type_def_aa8129ca70a2232c91c8cfcaf375249f6}\index{TIM\_TypeDef@{TIM\_TypeDef}!CCMR2@{CCMR2}}
\index{CCMR2@{CCMR2}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CCMR2}{CCMR2}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_aa8129ca70a2232c91c8cfcaf375249f6} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+CCMR2}

TIM capture/compare mode register 2, Address offset\+: 0x1C \Hypertarget{struct_t_i_m___type_def_ac0dcd8f9118b07b16cd79d03cb1a0904}\index{TIM\_TypeDef@{TIM\_TypeDef}!CCMR3@{CCMR3}}
\index{CCMR3@{CCMR3}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CCMR3}{CCMR3}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_ac0dcd8f9118b07b16cd79d03cb1a0904} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+CCMR3}

TIM capture/compare mode register 3, Address offset\+: 0x54 \Hypertarget{struct_t_i_m___type_def_a0dd9c06729a5eb6179c6d0d60faca7ed}\index{TIM\_TypeDef@{TIM\_TypeDef}!CCR1@{CCR1}}
\index{CCR1@{CCR1}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CCR1}{CCR1}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_a0dd9c06729a5eb6179c6d0d60faca7ed} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+CCR1}

TIM capture/compare register 1, Address offset\+: 0x34 \Hypertarget{struct_t_i_m___type_def_a4d1171e9a61538424b8ef1f2571986d0}\index{TIM\_TypeDef@{TIM\_TypeDef}!CCR2@{CCR2}}
\index{CCR2@{CCR2}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CCR2}{CCR2}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_a4d1171e9a61538424b8ef1f2571986d0} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+CCR2}

TIM capture/compare register 2, Address offset\+: 0x38 \Hypertarget{struct_t_i_m___type_def_ac83441bfb8d0287080dcbd945a272a74}\index{TIM\_TypeDef@{TIM\_TypeDef}!CCR3@{CCR3}}
\index{CCR3@{CCR3}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CCR3}{CCR3}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_ac83441bfb8d0287080dcbd945a272a74} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+CCR3}

TIM capture/compare register 3, Address offset\+: 0x3C \Hypertarget{struct_t_i_m___type_def_a5ba381c3f312fdf5e0b4119641b3b0aa}\index{TIM\_TypeDef@{TIM\_TypeDef}!CCR4@{CCR4}}
\index{CCR4@{CCR4}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CCR4}{CCR4}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_a5ba381c3f312fdf5e0b4119641b3b0aa} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+CCR4}

TIM capture/compare register 4, Address offset\+: 0x40 \Hypertarget{struct_t_i_m___type_def_af30dc563e6c1b7b7e01e393feb484080}\index{TIM\_TypeDef@{TIM\_TypeDef}!CCR5@{CCR5}}
\index{CCR5@{CCR5}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CCR5}{CCR5}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_af30dc563e6c1b7b7e01e393feb484080} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+CCR5}

TIM capture/compare register5, Address offset\+: 0x58 \Hypertarget{struct_t_i_m___type_def_a374f851b5f1097a3ebd3f494ded6512a}\index{TIM\_TypeDef@{TIM\_TypeDef}!CCR6@{CCR6}}
\index{CCR6@{CCR6}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CCR6}{CCR6}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_a374f851b5f1097a3ebd3f494ded6512a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+CCR6}

TIM capture/compare register6, Address offset\+: 0x5C \Hypertarget{struct_t_i_m___type_def_a6fdd2a7fb88d28670b472aaac0d9d262}\index{TIM\_TypeDef@{TIM\_TypeDef}!CNT@{CNT}}
\index{CNT@{CNT}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CNT}{CNT}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_a6fdd2a7fb88d28670b472aaac0d9d262} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+CNT}

TIM counter register, Address offset\+: 0x24 \Hypertarget{struct_t_i_m___type_def_a9dafc8b03e8497203a8bb395db865328}\index{TIM\_TypeDef@{TIM\_TypeDef}!CR1@{CR1}}
\index{CR1@{CR1}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR1}{CR1}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_a9dafc8b03e8497203a8bb395db865328} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+CR1}

TIM control register 1, Address offset\+: 0x00 \Hypertarget{struct_t_i_m___type_def_a6b1ae85138ed91686bf63699c61ef835}\index{TIM\_TypeDef@{TIM\_TypeDef}!CR2@{CR2}}
\index{CR2@{CR2}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR2}{CR2}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_a6b1ae85138ed91686bf63699c61ef835} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+CR2}

TIM control register 2, Address offset\+: 0x04 \Hypertarget{struct_t_i_m___type_def_a7efe9ea8067044cac449ada756ebc2d1}\index{TIM\_TypeDef@{TIM\_TypeDef}!DCR@{DCR}}
\index{DCR@{DCR}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DCR}{DCR}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_a7efe9ea8067044cac449ada756ebc2d1} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+DCR}

TIM DMA control register, Address offset\+: 0x48 \Hypertarget{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef}\index{TIM\_TypeDef@{TIM\_TypeDef}!DIER@{DIER}}
\index{DIER@{DIER}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DIER}{DIER}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_a22a33c78ca5bec0e3e8559164a82b8ef} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+DIER}

TIM DMA/interrupt enable register, Address offset\+: 0x0C \Hypertarget{struct_t_i_m___type_def_afb7114ac49dba07ba5d250c507dbf23d}\index{TIM\_TypeDef@{TIM\_TypeDef}!DMAR@{DMAR}}
\index{DMAR@{DMAR}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DMAR}{DMAR}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_afb7114ac49dba07ba5d250c507dbf23d} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+DMAR}

TIM DMA address for full transfer, Address offset\+: 0x4C \Hypertarget{struct_t_i_m___type_def_a04248d87f48303fd2267810104a7878d}\index{TIM\_TypeDef@{TIM\_TypeDef}!EGR@{EGR}}
\index{EGR@{EGR}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{EGR}{EGR}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_a04248d87f48303fd2267810104a7878d} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+EGR}

TIM event generation register, Address offset\+: 0x14 \Hypertarget{struct_t_i_m___type_def_ad03c852f58077a11e75f8af42fa6d921}\index{TIM\_TypeDef@{TIM\_TypeDef}!PSC@{PSC}}
\index{PSC@{PSC}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PSC}{PSC}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_ad03c852f58077a11e75f8af42fa6d921} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+PSC}

TIM prescaler, Address offset\+: 0x28 \Hypertarget{struct_t_i_m___type_def_ad432e2a315abf68e6c295fb4ebc37534}\index{TIM\_TypeDef@{TIM\_TypeDef}!RCR@{RCR}}
\index{RCR@{RCR}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RCR}{RCR}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_ad432e2a315abf68e6c295fb4ebc37534} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+RCR}

TIM repetition counter register, Address offset\+: 0x30 \Hypertarget{struct_t_i_m___type_def_ad6bf779ed80e96e9b3bda4c2dc3a1a6b}\index{TIM\_TypeDef@{TIM\_TypeDef}!RESERVED1@{RESERVED1}}
\index{RESERVED1@{RESERVED1}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED1}{RESERVED1}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_ad6bf779ed80e96e9b3bda4c2dc3a1a6b} 
uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+RESERVED1}

Reserved, 0x50 \Hypertarget{struct_t_i_m___type_def_a67d30593bcb68b98186ebe5bc8dc34b1}\index{TIM\_TypeDef@{TIM\_TypeDef}!SMCR@{SMCR}}
\index{SMCR@{SMCR}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SMCR}{SMCR}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_a67d30593bcb68b98186ebe5bc8dc34b1} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+SMCR}

TIM slave mode control register, Address offset\+: 0x08 \Hypertarget{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff}\index{TIM\_TypeDef@{TIM\_TypeDef}!SR@{SR}}
\index{SR@{SR}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SR}{SR}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_acedfc978c879835c05ef1788ad26b2ff} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+SR}

TIM status register, Address offset\+: 0x10 \Hypertarget{struct_t_i_m___type_def_a48ce9972eb643ae4f34bd75a0b931ad4}\index{TIM\_TypeDef@{TIM\_TypeDef}!TISEL@{TISEL}}
\index{TISEL@{TISEL}!TIM\_TypeDef@{TIM\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TISEL}{TISEL}}
{\footnotesize\ttfamily \label{struct_t_i_m___type_def_a48ce9972eb643ae4f34bd75a0b931ad4} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t TIM\+\_\+\+Type\+Def\+::\+TISEL}

TIM Input Selection register, Address offset\+: 0x68 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
